1. Field of the Invention
The present invention relates to a wiring connection structure of a laminated capacitor and a decoupling capacitor, and a wiring board. The present invention particularly relates to a laminated capacitor that is advantageously applied to a high frequency circuit, and a wiring connection structure of a decoupling capacitor constructed using the laminated capacitor, and wiring boards.
2. Description of the Related Art
Most typical conventional laminated capacitors include a capacitor body having a plurality of laminated dielectric layers having, for example, ceramic dielectrics, and plural pairs of first and second internal electrodes alternately disposed along the direction of lamination of the dielectric layers in opposed relation with each other so as to define a plurality of capacitor units. First and second external terminal electrodes are provided on the first and second end surfaces, respectively, of the capacitor. The first internal electrodes extend onto the first end surface of the capacitor body, where the first internal electrodes are electrically connected to the first external terminal electrodes. The second internal electrodes are also extended onto the second end surface, where the second internal electrodes are electrically connected to the second external terminal electrodes.
In this laminated capacitor, the electric current flowing, for example, from the second external terminal electrode to the first external terminal electrode flows from the second external terminal electrode to the second internal electrode, and arrives at the first internal electrode from the second internal electrode through the dielectric layer, followed by arriving at the first external electrode through the first internal electrode.
The equivalent circuit of a capacitor is represented by a circuit in which C, L and R are connected in series, where C denotes the capacitance of the capacitor, L denotes an equivalent series inductance (ESL) and R denotes an equivalent series resistance (ESR) mainly defined of the resistance R of the electrode.
The resonance frequency (f0) of this equivalent circuit is represented by an equation of f0=1/[2π×(L×C)1/2], which means that the function as a capacitor is lost at a higher frequency than the resonance frequency. In other words, the resonance frequency (f0) becomes high when the value of L, or the value of ESL, is small, to allow the capacitor to be available at higher frequencies. Although copper has been used for forming the internal electrode in order to reduce the ESR value, a capacitor designed to have a low ESR value is required for applying the capacitor in microwave regions.
A low ESR value is also required for the capacitor to be used as a decoupling capacitor, which is connected to a power supply circuit for supplying electricity to a MPU chip (a bear chip) of a microprocessing unit (MPU) for a work station or a personal computer.
FIG. 8 is a block diagram illustrating one example of the wiring connection structure of a MPU 1 and a power source 2 as described above.
With reference to FIG. 8, the MPU 1 includes a MPU chip 3 and a memory 4. The power source 2 is provided to supply electricity to the MPU chip 3, and a decoupling capacitor 5 is connected to the power supply circuit including the MPU chip 3 to the power source 2. A signal circuit is provided in the area from the MPU chip 3 to the memory 4.
The decoupling capacitor 5, which is used in conjunction with the MPU 1, is also used for absorbing noises or smoothing fluctuation of the power source in the same way as conventional decoupling capacitors are used. However, use of a decoupling capacitor having operating frequencies of over 500 MHz and up to 1 GHz have been recently contemplated in a MPU chip 3, which is required to have a function as a quick power supply (a function to supply electric power from the charged electricity of a capacitor within a time interval of several nano-seconds, when electricity is urgently needed for power-up of the system), when a high speed operation is required with respect to the MPU chip 3.
The power source is actually designed so that a DC power of about 2.0 V is supplied to the MPU chip 3 (with an operation clock frequency of about 500 MHz) with a power consumption of about 24 W, or an electric current of 12 A. For reducing power consumption, the system is configured to put the system in a sleep mode when the MPU chip 1 is on alert, thereby reducing the power consumption to 1 W or less. Electric power required for converting the system from the sleep mode to the active mode should be supplied to the MPU chip 3 within a time interval of the operating clock frequency, or the electric power should be supplied to the CPU within a time interval of about 4 to about 7 nano-seconds at an operation frequency of 500 MHz for converting the system from the sleep mode to the active mode.
However, because the supply of the electric power from the power source 2 is too late, the MPU chip 3 has been powered by discharging the electricity accumulated in the decoupling capacitor 5 placed in the vicinity of the MPU chip 3 before the electricity is supplied from the power source 2.
Accordingly, the inductance component has been desired to be as low as possible in the decoupling capacitor 5 for the MPU 1, urging development of a capacitor having a very low inductance value.
Under the conditions described above, a wiring structure of a laminated capacitor that is able to lower the ESL value has been proposed in Japanese Unexamined Patent Publication No. 11-204372.
The ESL value is mainly reduced by offsetting magnetic fields induced by the electric current flowing in the laminated capacitor. Therefore, the electric current is allowed to flow along various directions in the laminated capacitor in order to offset the magnetic fields. For diversifying the current directions, the number of the external terminal electrodes provided on the surface of the capacitor body is increased, or the number of externally exposed terminal tabs of the internal electrodes to be electrically connected to the external terminal electrodes is increased, besides shortening the flow path length of the current flowing through the internal electrodes.
FIG. 9 illustrates a laminated capacitor 11 disclosed in the foregoing Japanese Unexamined Patent Application Publication No. 11-204372 together with an illustration of the cross-sectional structure of a MPU 12 using the laminated capacitor 11 as a decoupling capacitor.
With reference to FIG. 9, the laminated capacitor 11 is provided with a capacitor body 14 including a plurality of laminated dielectric layers 13. At least one pair of first and second internal electrodes 15 and 16 arranged opposite to each other with specified layers of the dielectric layer 13 disposed therebetween are provided within the capacitor body 14.
Both of first and second external electrodes 18 and 19 are provided on the first major surface 17 of the capacitor body 14 extending substantially parallel to the internal electrodes 15 and 16. External terminal electrodes are not provided at all on a second major surface 20 which is opposite to the first major surface 17.
First feedthrough conductors 21, which perforate through specified layers of the dielectric layers 13 so as to provide electrical continuity between the first internal electrodes 15 and the first external terminal electrodes 18 while the electrodes are electrically insulated from the second internal electrode 16, and second feedthrough conductors 22, which perforate through specified layers of the dielectric layer 13 so as to provide electrical continuity between the second internal electrodes 16 and the second external terminal electrodes 19 while the electrodes are electrically insulated from the first internal electrodes 15, are provided within the capacitor body 14.
A plurality of the first and second feedthrough conductors 21 and 22 are provided, and a plurality of the first and second external terminal electrodes 18 and 19 are also provided corresponding to positions of the respective first and second feedthrough conductors 21 and 22.
According to the laminated capacitor 11 as described above, the magnetic fields induced by the electric current flowing through the internal electrodes 15 and 16 offset each other to lower the ESL value, since the directions of the electric current flowing through the internal electrodes 15 and 16 are diversified in addition to the flow path being shortened.
The MPU 12 includes, on the other hand, a multi-layered wiring board 24 having a cavity 23 on the bottom surface thereof. A MPU chip 25 is mounted on the surface of the wiring board 24. The laminated capacitor 11 that defines a decoupling capacitor is accommodated within the cavity 23 of the wiring board 24. The wiring board 24 is mounted on the surface of a mother board 26.
As illustrated in the drawing, wiring conductors required for the MPU 12 are arranged within and on the surface of the wiring board 24, and an electrical circuit as shown in FIG. 8 is completed by these wiring conductors.
A representative example includes hot-side electrodes 27 for a power source and ground electrodes 28 disposed within the wiring board 24.
The hot-side power electrode 27 is electrically connected to the first external terminal electrode 18 of the laminated capacitor 11 through a via-hole conductor 29 at the hot side for the power source, is electrically connected to a specified terminal 31 of the MPU chip 25 through a via-hole conductor 30 at the hot side of the power source, and is electrically connected to a hot-side conductive land 33, which is destined to be in electrical continuity with the mother board 26, through a via-hole conductor 32 at the hot side for the power source.
The ground electrode 28 is electrically connected to the second external terminal electrode 19 of the laminated capacitor 11 through a via-hole conductor 34 for grounding, is electrically connected to a specified terminal 36 of the MPU chip 25 through a via-hole conductor 35 for grounding, and is electrically connected to a conductive land 38 for grounding, which is destined to be connected to the mother board 26, through a via-hole conductor 37 for grounding.
Illustration of the memory corresponding to the memory 4 shown in FIG. 8 is omitted in FIG. 9.
Both of the first and second external terminal electrodes 18 and 19 are located on the major surface 17 of the capacitor body 14 in the laminated capacitor 11 as shown in FIG. 9. For example, if the wiring conductor has a ground potential, then the second external terminal electrode 19 of the capacitor 11 is connected to the conductive land 38 for grounding after passing through the via-hole 34 for grounding, the via-hole conductor 34 for grounding, the ground electrode 28 and the via-hole conductor 37 for grounding in the wiring board 24.
Accordingly, the length of the ground side line determined by the lengths of the via-holes conductors 34 and 37 for grounding, and the length of the ground electrode 28 turns out to be relatively longer so as to increase the inductance component generated around the ground side line. As a result, the effect of using the laminated capacitor 11 designed to have a low ESL value is compromised and reduced. The relatively longer ground side line also causes an increase of impedance.
Increasing of the length of the ground side line as described above also causes the wiring in the wiring board 24 to be very complicated.